Electronic devices, such as processors, memory components, controllers, signal converters, and other integrated circuits (ICs) are commonly found in electronic systems such as desktop, mobile, and hand-held computers. These electronic devices contain storage circuits, such as latches, flip-flops, and registers, that are connected to each other by signal lines that enable one storage circuit to communicate with another. Signal lines carry different types of signals such as data and clock signals. A data signal line carries data signals, including, for example, address, data, or control information, and a clock signal line carries clock signals. A clock signal is a signal that controls the operation of a circuit by synchronizing the time intervals during which data signals can be communicated from one storage circuit to another.
It is important that a data signal from a first storage circuit to a second, sequential storage circuit, traveling along a data signal line, is delayed long enough to ensure that the data signal does not reach the second storage circuit before the clock signal to the second storage circuit properly gates the data signal at the input to the second storage circuit. Otherwise, data may be lost. Delay on the data signal line is increased by, for example, placing delay elements, such as inverters, logic gates, or other buffers, on the data signal line to impede the path of the data signal communicated along the data signal line.
It is important that the number of delay elements placed on the data signal line to delay the data signal is not so excessive that the data signal is delayed much beyond the minimum amount of time that is necessary to preserve data integrity because excess delay elements needlessly increases the size and cost of the electronic device. In addition, the speed of communication between the two sequential storage circuits will be unduly slowed by excess delay elements, potentially slowing the speed of the electronic device.
The proper balance must be struck between increasing the delay on the data signal line between a first storage circuit and a second storage circuit to delay the data signal to allow the clock signal enough time to properly gate the second storage circuit, versus reducing the number of delay elements on the data signal line to increase the speed of communication and reduce needless circuitry between the two storage circuits. Striking the proper balance between these two competing interests serves to both improve the reliability and reduce the size of the overall electronic device. In doing so, the reliability and size of electronic systems, such as computers, is improved, and cost is reduced.
It is the job of the circuit designer to verify proper communication between two sequential storage circuits by ensuring that the data signal on the data signal line between the two storage circuits is delayed long enough to preserve data integrity. This verification is typically done during circuit simulations, before the electronic device is actually manufactured. Because this verification is done during simulation, the exact amount of delay that is minimally necessary to ensure proper communication between two circuits cannot be known, and is therefore estimated based on the layout of the circuit, the frequency of the clock, the manufacturing process, and other factors. Verifying that the proper amount of data signal delay is included on a data signal line between two circuits to ensure proper communication and to preserve data integrity between the two circuits is called minimum delay or "mindelay" checking or verification, or "hold time" checking or verification.
Estimating the minimum delay time necessary to ensure proper communication between two circuits can be difficult. If the minimum delay time selected is overly conservative or pessimistic (i.e. the minimum delay time is too long), the data signal line between the two circuits will be designed with too many delay elements, thereby needlessly increasing the size and cost of the electronic device. However, if the minimum delay time selected is too short (or optimistic), the data signal line between the two circuits will be designed with too few delay elements, making the data signal too fast, thereby reducing data integrity and causing the electronic device to malfunction. What is desired is a methodology for verifying proper communication between two, sequential, timed, circuits that strikes a proper balance between these two competing interests.